PLLs can be used, for example, for realizing frequency synthesizers of cellular phones. In a cellular phone, a frequency synthesizer is an essential part of a radio receiver integrated circuit (IC) and of a radio transmitter IC.
A typical PLL comprises, connected to each other in a loop in this order, a voltage controlled oscillator (VCO), a programmable frequency divider, a phase detector, a charge pump and a loop filter.
The VCO transforms a low frequency control voltage, in particular a direct-current (DC) control voltage, into a radio frequency (RF) signal. A change of the control voltage is reflected in a change of frequency of the generated RF signal in accordance with the gain of the VCO. The frequency of the signal output by the VCO is divided by a factor currently set in the programmable frequency divider. The phase comparator then compares the phase of the resulting frequency divided signal with the phase of a reference signal, and outputs a signal representing the detected phase difference. The charge pump generates current impulses, the length of which are controlled by the output signal of the phase detector. The generated current pulses are filtered by the loop filter, which provides a corresponding DC control voltage to the VCO and thus takes care that the VCO generates a signal which is locked to a desired frequency.
The frequency of the RF signals output by the VCO can be changed by changing the division ratio applied by the programmable divider.
The loop filter of the PLL may be active or passive and is typically some kind of an RC-filter. It includes at least one capacitor storing the driving DC control voltage for the VCO in order to ensure a stable supply of the DC control voltage to the VCO.
When the division ratio applied by the frequency divider is changed in order to change the frequency of the VCO output signal, the phase detector detects suddenly a large phase difference between the frequency divided VCO output signal and the reference signal. As a result, the voltage over the capacitor of the loop filter changes rapidly. In the dielectric insulator layer of a capacitor, there exists a physical phenomenon called dielectric absorption. The dielectric absorption is a consequence of a slowness of molecule dipoles in a dielectric material. After a rapid voltage change, the phenomenon tends to partly move the voltage across the capacitor back to the original value.
FIG. 1 presents a model of the dielectric absorption of a capacitor C11. The model includes a resistor-capacitor (RC) circuit, comprising a series connection of a resistor R11 and of a capacitor C12, which is arranged in parallel with the actual capacitor C11. The RC circuit causes the parasitic side effect.
For external, non-integrated loop filters, solid capacitors of the np0 type are available, for which the dielectric absorption is at a level that PLL settling time specifications can be met. This kind of capacitor cannot be integrated, however, so this solution is expensive.
In highly dielectric capacitors, in contrast, which are used in modern integrated circuits, the effect of the dielectric absorption is significant. In the case of integrated capacitors, the time constant of the parasitic RC circuit depicted in FIG. 1 can be some milliseconds or even more. This makes a PLL equipped with such a capacitor too slow for some applications, for instance for a usage in a cellular phone.
In U.S. patent application 2004/0100311 A1, the problem of the dielectric absorption of PLL loop filter capacitors in conjunction with the change in the tuning voltage of a PLL is addressed as well. In this document, it is proposed to compensate for the memory effect of the loop filter capacitors by means of a resonant frequency pre-selection in the VCO. To this end, the VCO has a frequency-determining capacitance controlled through a second tuning input. It is proposed that this capacitance is controlled by the same frequency word as the frequency divider such that a change in the tuning voltage upon a change in the frequency word is as small as possible.
It is a disadvantage of such an approach that the accuracy may not be satisfactory due to the fact that a PLL includes many variables that cannot be predicted by reading the divider input. This applies in particular to component variations and thermal drifts. The resulting system thus needs a lot of frequency overlapping between each rough step. As a consequence, the design of the most critical components, for example the VCO, becomes very difficult. Further, the window in which the system is able to tune the VCO might be too large to avoid the memory effect.